{
 "id": "ESCAD/OpenRTLSet",
 "owner": "ESCAD",
 "name": "OpenRTLSet",
 "downloads": 274,
 "likes": 2,
 "last_modified": "2026-06-08T00:26:38.000Z",
 "stated_licence": "apache-2.0",
 "stated_from": "tag",
 "licence_name": null,
 "licence_link": null,
 "file_licence": null,
 "licence_files": [],
 "sources": [],
 "gated": false,
 "tasks": [
  "text-generation"
 ],
 "citation": "Please cite using the following bibtex entry:\n\n```\n@inproceedings{wang2025openrtlset,\n  title={{OpenRTLSet}: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design}, \n  author={Wang, Jinghua and Wan, Lily Jiaxin and Pingali, Sanjana and Smith, Scott and Jha, Manvi and Sivakumar, Shalini and Zhao, Xing and Cao, Kaiwen and Chen, Deming},\n  booktitle={2025 IEEE International Conference on LLM-Aided Design (ICLAD'25)}, \n  year={2025}\n}\n```",
 "signal": "permissive",
 "reason": "The declared licence (apache-2.0) is classified as permissive.",
 "revision": "e2bf571c4a3f31016936dc264678eb97ecd414c6",
 "stated_evidence": "https://huggingface.co/datasets/ESCAD/OpenRTLSet/blob/e2bf571c4a3f31016936dc264678eb97ecd414c6/README.md",
 "file_evidence": "https://huggingface.co/datasets/ESCAD/OpenRTLSet/tree/e2bf571c4a3f31016936dc264678eb97ecd414c6",
 "card_nc": false
}