{
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 "owner": "Navyandsu",
 "name": "Verilog_VL",
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 "last_modified": "2025-04-03T05:30:01.000Z",
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 "citation": "<!-- If there is a paper or blog post introducing the dataset, the APA and Bibtex information for that should go in this section. -->\n\n**BibTeX:**\n\n[More Information Needed]\n\n**APA:**\n\n[More Information Needed]",
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}