{
 "id": "Pengwei-Jin/RealBench",
 "owner": "Pengwei-Jin",
 "name": "RealBench",
 "downloads": 556,
 "likes": 1,
 "last_modified": "2026-07-14T11:48:35.000Z",
 "stated_licence": null,
 "stated_from": "none",
 "licence_name": null,
 "licence_link": null,
 "file_licence": "mit",
 "licence_files": [
  "LICENSE"
 ],
 "sources": [],
 "gated": false,
 "tasks": [],
 "citation": "@article{jin2025realbench,\n  title={RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs},\n  author={Jin, Pengwei and Huang, Di and Li, Chongxiao and Cheng, Shuyao and Zhao, Yang and Zheng, Xinyao and Zhu, Jiaguo and Xing, Shuyi and Dou, Bohan and Zhang, Rui and others},\n  journal={arXiv preprint arXiv:2507.16200},\n  year={2025}\n}",
 "signal": "unclear",
 "reason": "The checks could not identify a recognised licence ID in the dataset's metadata.",
 "revision": "f238db3da859557ab5d0a0877b608c3a303a7455",
 "stated_evidence": "https://huggingface.co/datasets/Pengwei-Jin/RealBench/blob/f238db3da859557ab5d0a0877b608c3a303a7455/README.md",
 "file_evidence": "https://huggingface.co/datasets/Pengwei-Jin/RealBench/blob/f238db3da859557ab5d0a0877b608c3a303a7455/LICENSE",
 "card_nc": false
}