{
 "id": "develoco/PyraNet-Verilog",
 "owner": "develoco",
 "name": "PyraNet-Verilog",
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 "last_modified": "2026-06-17T22:25:18.000Z",
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 "tasks": [
  "text-generation",
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 "citation": "@INPROCEEDINGS{11133406,\n  author={Nadimi, Bardia and Boutaib, Ghali Omar and Zheng, Hao},\n  booktitle={2025 62nd ACM/IEEE Design Automation Conference (DAC)}, \n  title={PyraNet: A Multi-Layered Hierarchical Dataset for Verilog}, \n  year={2025},\n  volume={},\n  number={},\n  pages={1-7},\n  keywords={Codes;Design automation;Accuracy;Large language models;Transformers;Hardware design languages;Large Language Models;fine-tuning;Verilog;dataset;transformers},\n  doi={10.1109/DAC63849.2025.11133406}}",
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