{
 "id": "jpate190/VeriLM-instruct-pairs",
 "owner": "jpate190",
 "name": "VeriLM-instruct-pairs",
 "downloads": 10,
 "likes": 0,
 "last_modified": "2026-08-03T01:01:48.000Z",
 "stated_licence": "bigcode-openrail-m",
 "stated_from": "tag",
 "licence_name": null,
 "licence_link": null,
 "file_licence": null,
 "licence_files": [],
 "sources": [
  {
   "id": "shailja/Verilog_GitHub",
   "licence": "mit",
   "found": true,
   "evidence": "https://huggingface.co/datasets/shailja/Verilog_GitHub/blob/15420106f9ebc5a7596d0f5b95f3bfbc5db18219/README.md"
  }
 ],
 "gated": false,
 "tasks": [
  "text-generation"
 ],
 "citation": "@article{thakur2024verigen,\n  author  = {Thakur, Shailja and Ahmad, Baleegh and Pearce, Hammond and Tan, Benjamin and Dolan-Gavitt, Brendan and Karri, Ramesh and Garg, Siddharth},\n  title   = {VeriGen: A Large Language Model for Verilog Code Generation},\n  journal = {ACM Transactions on Design Automation of Electronic Systems},\n  volume  = {29}, number = {3}, articleno = {46}, year = {2024},\n  doi     = {10.1145/3643681}, url = {https://doi.org/10.1145/3643681}\n}\n\n@misc{patel2026verilminstructpairs,\n  author = {Patel, Jal},\n  title  = {VeriLM Instruction Pairs},\n  year   = {2026},\n  url    = {https://huggingface.co/datasets/jpate190/VeriLM-instruct-pairs}\n}",
 "signal": "unclear",
 "reason": "The checks could not identify a recognised licence ID in the dataset's metadata.",
 "revision": "1b4da7d02ba32d0215bb1a18d603eddffe71c36e",
 "stated_evidence": "https://huggingface.co/datasets/jpate190/VeriLM-instruct-pairs/blob/1b4da7d02ba32d0215bb1a18d603eddffe71c36e/README.md",
 "file_evidence": "https://huggingface.co/datasets/jpate190/VeriLM-instruct-pairs/tree/1b4da7d02ba32d0215bb1a18d603eddffe71c36e",
 "card_nc": false
}